Digital watch having dual purpose ring counter

ABSTRACT

An electronic digital watch having at least three multiplexed display digits timed directly with signals generated by the frequency divider chain used to produce the usual one cycle per minute or one cycle per second time base.

DIGITAL WATCH HAVING DUAL PURPOSE RING COUNTER OTHER PUBLICATIONS R.C. St. John, Frequency Divide by Three Circuit,

I751 lnvemo i New?Ort Beach IBM Technical Disclosure Bulletin, Vol. 15. No. 9,

Cahf- Feb. 1973, pp. 2717 & 2718. [73] Assignee: Hughes Aircraft Company, Culver City, Calif. Primary Examiner-L. T. HiX Assistant ExaminerU. Weldon [22] Flled' 1974 Attorney, Agent, or FirmJoseph E. Szabo; [2]] Appl. N0.: 435,914 MacAllister [52] US. Cl. 58/23 R; 58/50 R [57] ABSTRACT [51] Int. Cl. G04C 3/00 An electronic di gltal watch having at least three multi- Fleld Of Search R. 38, plexed timed directly Signals g 340/336 235/92 R ated by the frequency divider chain used to produce the usual one cycle per minute or one cycle per sec- [56] References Cited 0nd time base UNITED STATES PATENTS 3,392,270 7/1968 Boucke 235/92 R 6 6 Dmwmg F'gures f I 0' d t/M |7\ 2| IVI e D 'd f/3M D /3 I by M b y Tiiree b'I'N" M 32232 l B J 3 l l-l l-l r 4L LJ 1A B Data c Digit Select 25 l l l l Decoder Display Drivers Display Digit Select US. Patent Nov.25, 1975 Sheet30f5 3,921,384

+ 3 5 Eot US. Patent Nov. 25,1975 SheetSofS 3,921,384

DIGITAL WATCH HAVING DUAlL PURPOSE RING COUNTER BACKGROUND OF THE INVENTION The present invention relates generally to digital watches, and more particularly to such watches having multiplexed display digits actuated by electronic storage registers in which signals representing different units of time are accumulated and periodically updated in response to a relatively low frequency signal such as one cycle per minute. The low frequency time base signal is usually derived from a high frequency quartz crystal time base through a frequency divider.

In watches of the above type, particularly those using light-emitting diode (LED) display digits. it has been customary heretofore to derive the multiplexing signals for timing the respective display digits from signals produced by the frequency divider by means of a separate counter or by means of an array of logic gates. Exemplary of these approaches are Walton U.S. Pat. No. 3,707,071 and Dargent U.S. Pat. No. 3,760,584.

The purpose of the present invention is to simplify the construction of digital electronic watches having multiplexed display digits by using the dividing chain to generate the display multiplexing signals directly. In accordance with the invention as applied to a digital watch having three multiplexed display digits, each assigned to indicate a different unit of time, a high frequency timing signal is divided down to form a time base signal of no lower frequency than one cycle per minute. This is accomplished by a chain of dividers built with binary elements which includes a divide-bythree subcircuit generating three differently phased timing signal trains. The time base signal is converted into a separate binarily coded signal set to represent each signaled unit of time such as units-of-minutes. tens-of-minutes, units-of-hours. etc. Then, by means controlled by the three timing signal trains. each display digit is energized in turn with a decoded translation of the binarily coded signal set representing the unit of time assigned to that digit.

Advantageously, the divide-by-three counter is comprised of three cascaded, single stage shift registers and a single complex logic gate connected so as to limit the possible combination of their logic states to three. In keeping with the invention as illustrated herein. the complex gate is the logical equivalent of a pair of AND gates whose outputs are applied to the inputs of a NOR gate. The inputs to the complex gate are the shift register outputs. and the output of the complex gate is applied to the set or reset input of the shift registers. The AND gate inputs are chosen so that the AND gates are operative to detect five undesirable combinations of states out of the possible total of eight combinations of states which the three shift registers could assume. Furthermore. the AND gates are operative to cause the shift registers to be shifted out of these five combinations of undesirable states into one of the remaining three combinations of states which are deemed to be desirable.

Further advantages and objects of the invention will become apparent by reference to the figures in which:

FIG. 1 is a block diagram of a digital watch incorporating features of the present invention; I

FIG. 2 is a detailed schematic diagram of the watch illustrated generally in FIG. I, said diagram being formed by combining FIGS. 211-211: and

FIG. 3 is a table illustrating the eight possible combinations of states which the shift registers of the present invention may assume and the manner in which five undesirable ones of these combinations are detected by logic gates and are eliminated by them.

Turning to the figures, a block diagram of a digital watch. using the present invention. is shown in FIG. 1. Pulses generated by a quartz crystal oscillator II are divided by a chain of dividers 13 to a low frequency time base. such as one cycle per minute. It will be understood that. if it were desirable to display seconds. the time base would typically be one cycle per second. The one cycle per minute time base is applied to a set of minutes and hours counters 21 which are stepped by each pulse of the time base into a successive stable state in which they represent a unique combination of minutes and hours until they are stepped to the next such state. The outputs of the counters 2] produce a set of binary coded decimal signals which also change with each pulse of the time base and represent the existing time.

The binary coded decimal signals produced by the counters 21 are applied to a decoder 25 through a set of data digit select gates 23 whose function is to apply signals produced by counters representing different units of time to the decoder in succession. Thus. in the case of three counters respectively representing unitsof-minutes. tens-of-minutes. and units-of-hours. it is the function of the data digit select gates 23 to apply the outputs of respective ones of those three sets of counters to the decoder 25 in succession. The decoder 25 converts the binary coded decimal outputs fed to it into a seven segment-compatible form. wherein desired ones of seven output lines of the decoder are energized in response to binary coded decimal signals. A suitable decoder for this purpose is described and claimed in application Ser. No. 373.569 by the present applicant. filed on June 25. 1973, and entitled. Segment Decoder for Numeric Display, which is incorporated by this reference.

By means of a set of seven display drivers 27, the seven segment-compatible signals from the decoder 25 are applied to the segments of a set of seven segment display digits 29. As will be explained in greater detail hereinafter. the tens-of-hours digit is treated differently from the other three display digits and is energized separately from them. The last three digits of the display 29 are concurrently energized by the display drivers 27 so that if, for example, a numeral eight is binarily signaled at the inputs of the decoder 25, all seven of its outputs are energized and all seven segments of the last three display digit 29 are signaled by the display drivers 27.

In order to cause only that digit to glow which corresponds to the counter from which the energizing binary coded decimal sigmtls-originated. the digit must also be enabled by a set of display digit select gates 31. To cause the proper digit 29 to glow. the display digit select gates 3] are actuated in synchronism with the data digit select gates 23 so that gates in the groups 23 and 3] associated with a given unit of time are actuated in synchronism. Toward this end. strobing signals A. B. and C are derived from the frequency divider l3 and are applied to both sets of gates 23 and 31 so that they will be switched in synchronism.

The foregoing organization has been generally used in digital watches. In accordance with the present invention, however, contrary to known digital watches.

the strobing signals A. B. and C are derived directly from the stages of the dividers 13. This is achieved by selecting the frequency of the oscillator 11 so that the factor by which that frequency needs to be divided'by the divider 13 to arrive at a suitable time base. such as one cycle per minute. includes a factor of three. In further keeping with the invention. having selected the oscillator frequency 11 in this manner. the frequency-divider 13 is so constituted as to include among its stages a divide-by-three counter operating at a sufficiently high frequency in the chain of counters 13 to generate signals which are at a high enough frequency to be utilized for strobing the display digits without such strobing becoming visible. For those reasons, there is interposed between the divide-by-three counter 17 and the minutes and hours counters 21 a divide-by-N counter 19. Similarly. in order to allow the strobing to take place at a frequency lower than that of oscillator 11. divide-by-M counter 15 is interposed between the oscillator and divide-hy-three counter 17. Thus. assuming that the oscillator 11 produces a frequency f. the input ofthe divide-by-three counter will be flM. the output of the divide-by-three counter 17 will be f/3M and the input of the minutes and hours counters 21 is f/3MN.

In accordance with the present invention. the divideby-three circuit 17 .servesnot only to contribute to the dividing down of the oscillator frequency 11 to the time base frequency. but also to directly generate the three strobing signals A. B. and C which are characterized by the fact that each of them occupies one-third of the time period of their complete cycle.

In this manner the strobing signals A. B. and C cause each of the units-of-hours. tens-of-minutes. andunitsof-minutes signals to be displayed one-third of the time in rapidly cycling succession on their respective display I digits 29.

A detailed circuit diagram of an exemplary digital watch incorporating the present invention is shown in FIGS. 2a-2d. The timekeeping element of the watch is the oscillator 11 shown as operating at a precise frequency of 786.432 hertz. Such oscillators are wellknown in the art and usually use a quartz crystal as part of the oscillator circuit. It might be noted at this point that all of the elements shown in FIGS. 2u2zl except for the quartz crystal. some oscillator passive or timing components. and the display elements are preferably constructed of C MOS circuitry and fabricated as a single large scale integrated (LSl) circuit. Pulses from the oscillator 11 are divided down to a time base frequency of one cycle per minute by the frequency divider 13,

shown as comprising three major portions. Central to i the present invention is the intermediate divider portion 17 which is operative to cut down by a factor of three the frequency of the signal it receives. lnterposed between the divide-by-three circuit 17 and the oscillator 11 is the first portion of the divider 13 which is effective to divide the frequency received from the oscillator 11 by a factor of 2 or L024. The details of the divide-by-l.024 circuit are not shown since its construction is well within the skill of those in the digital watch art. It would typically comprise a ten-stage binary-divider comprising ten cascaded toggle flip-flops.

The significance of dividing by 1.024 is simply that the operating frequency of the divide-by-three counter 17 is thereby brought down to a range which is suitable for mulitplexing the display 29. Consequently, if for some reason the frequency of the oscillator 11 were raised or lowered from that shown. the factor by which 4 the circuit 15 divides would probably be changed correspondingly, assuming that the desired frequency for multiplexing the display-29 remains unchanged.

Having divided the input signal by a factor of three. the circuit 17 feeds pulses at a rate of 256 Hz to a divide-by-Z" or 256. circuit 190 whose output is therefore 1 Hz. The divide-by-Z" circuit 19a is not shown in detail since its construction is also well known to those skilled in the art. lt may be thesame type of binary divider as that which would be used for constructing the divideby-?. circuit 15. Preferably. however. in a manner also known. the divide-by-Z" circuit 19a will be formed of static stages whereas the divide-by-Z circuit will be comprised primarily of dynamic counter stages. Dynamic counter stages draw less current but have a minimum operating frequency. hence their use at the high frequency end of the frequency divider 13. They cannot be used reliably at the lower frequency end where the divider 19a operates because of inherent limitations of such types of circuits.

A divide-by-6O circuit 19b converts the 1 Hz output of the dividing circuit 19a into the desired one pulse per minute time base for driving the minutes counters 21a. The minutes counter 21a is comprised of two sets of T flip-flops. The first set 33-1 through 33-8 registers units-of-minutes. and the second set 35-1 through 35-4 represents the tens-of-minutes. In operation, time base pulses from the divide-by-6O circuit 19b are applied to the 4) input of the first flip-flop 33-1 through an input inverter 41 and a second inverter 43 in series therewith. The inverse of the signalbeing applied to the da input is applied to the 05 input through the same inverter 41 and a transmission gate 45. .The inverter 43 causes some delay in applying a logic level to the 05 input. The purpose of the transmission gate 45 is to cause the same delay to be incur ed in the inverse of the signal when it is applied to the (1) input of the flip-flop. T flip-flops are well knOVtl] in the art. being equivalent to a D flip-flop with the Q output connected to the D input and are characterized by the fact that each time the logic level at its d) input changes in a given direction (negative or positive) and the inverse of the change occurs at its 5 input. the logic levels of its Q and 6 outputs reverse from where they had been previous to the change at their clock inputs. Hence, with an alternating square wave input, its output is also an alternating square wave but at half the frequency. D flop-flops are commer- 'cially available as Model 4013 from RCA and other suppliers.

With each incoming time base pulse from the circuit 19b. that is once a minute. the count registered by the unit counters 33-1 through 33-8 is advanced by one. A NAND gate 47 detects logic ones at the outputs of the second and fourth flip-flops 33-2 and 33-8 and resets the counter. The output of gate 47 is thus a self-cancelling pulse. This pulse is also applied through an inverter 51 and through a line 53 to the d) and 4) inputs of the first flip-flop 35-1 of the tens-of-minutes counter portion. As a result. that flip-flop state is changed, thus causing an incrementation by l in the tens-of-minutes counter. The pulse also resets all of the flip-flops 33-1 through 33-8 in the units minutes counter. Subsequent 7 time base pulses through the inverter 41 again step the units counter flip-flops from 0 through 9 and on each tenth such pulse. the state of the tens counter is advanced by land the units counter is reset to 0.

When the sixtieth timing pulse is received. the tens counter flip-flops are reset by a NAND gate 55 which detects the presence of a 6 by a logic 1 being present at the Q outputs of t he flip-flops -2, 35-4. A reset pulse is applied to the R inputs of all of the tens counter flipflops through a line 56 connecting the output of the NAND gate 55 thereto. Just prior to the resetting just described, the units flip-flops 33-1 through 33-8 will have also become reset in response to the same signal which brought about the resetting of the tens flip-flops. A further effect of the sixtieth time base pulse received from the circuit 19b is the application of the output appearing at the the NAND gate 55 through the output inverter 57 of the minutes counter 21a to the hours counter 21b. lts units stages 37-1 through 37-8 are comprised of the same type of T flip-flops as those of the minutes counter 21a and operate in a very similar manner to progressively change binary states in response to incoming pulses. Thus, the first flip-flop 37-1 receives simultaneous inputs at its 4) and input terminals through an input inverter 61 and a transmission gate 63 which are together connected through common inverter 59 to the output of the output inverter 57 of the minutes counter 21a. These pulses arrive once each hour and cause the logic state of the first hours counter flip-flop 37-1 to reverse once each hour. Subsequent counter stages 37-2 through 37-8 could reverse their logic states every two, four, and eight hours respectively. After the tenth hourly input pulse to the hours counter 21b, its second, third, and fourth flip-flops 37-2 through 37-8 are reset by a signal derived from the Q outputs of the third and fourth flip-flops 37-4 and 37-8 by means f a NAND gate 65 whose output in turn is fed to the R inputs of all three flip-flops 37-2 through 37-8 through an inverter 67 and a NOR gate 69. The tenth pulse in addition to resetting 3 of the units flipflops also causes the tens flip-flop 39 to change its state from a logic 0 to a logic 1, thus registering a l therein. In this way, a binary coded decimal 10 is stored and registered in the counter 21b.

Arrival of the eleventh and twelfth pulses in the hours counter 21b is registered by the stepping of the first two flip-flops 37-1 and 37-2. The thirteenth pulse is registered by both of the flip-flops 37-1 and 37-2 going to binary l logic state which momentarily registers a 3. This is detected by a NAND gate 71 which also notes that there is a l in the tens flip-flop 39. Having thus detected the momentary registration of an undesirable 13 in the hours counter 21b, the NAND gate 71 output is applied to the reset input R of the tens flip-flop 39 and through an inverter 68 and the NOR gate 69 to the reset inputs of the units flip-flops 37-2, -4, and -8. As a result, these flip-flops are reset, leaving a 1 registered in the first flip-flop 37-1. Thus the decimal hour is l instead of the 13, which is the conventional manner of registering the thirteenth hour.

In all, there are four units of time being stored and signaled by the minutes counter 21a and the hours counter 21b. Of these, the first three, the units-ofminutes. the tens-of-minutes, and the units-of-hours are each signaled on a plurality of outputs in binary coded decimal form.'Thus, the units-of-minutes is signaled on four outputs, the tens-of-minutes on three, and the units-of-hours on four. The tens-of-hours is signaled on a single output connected to the Q terminal of its single flip-flop 39. The outputs of the units-of-minutes, tensof-minutes, and units-of-hours flip-flops need first to be selected and then decoded into a form of signal adapted to drive the multiplexeddisplay 29. For this purpose, they are applied to a set of transmission gates which lead to a seven-segment decoder 25 which is time shared to successively convert the binary coded decimal outputs of the three counter groups to a sevensegment format. Thus, the outputs of the units-ofminutes counter flip-flops 33-1 through 33-8 are applied through a set of four transmission gates 73 over lines -1 through 85-8 and inverters 87-1 through 87-8 to the inputs of the decoder 25 at certain selected times. These times are determined by the strobing signals produced in accordance with the present invention by the divide-by-three circuit 17 and are applied over line 950 to the P-channel MOSFET of each of the four transmission gates 73 and through an inverter 75 to the N-channel MOSFETs of the same transmission gates.

In response to the application of a logic 1 signal to the N-channel MOSFET gate and a logic 0 signal to the P-channel MOSFET gate. each transmission gate 73 is operative to transmit the signal being applied to its input by its associated flip-flop 33 to the seven-segment decoder 25.

Similar sets of transmission gates 77 and 81 serve to apply at appropriate times the outputs of the tens-ofminutes and the units-of-hours flip-flops to the sevensegment decoder 25. Thus. the B strobing signal is applied over line b to the transmission gate 77 with the aid of an inverter 79 and the strobing signal A is applied over line 95a to the transmission gate 81 by an aid of an inverter 83. Since there are only three flip-flops serving to register tens-of-minutes, there are only three transmission gates 77 associated with them. lt is to compensate for the lack of a fourth transmission gate in the group 77 that a P-channel MOSFET 84 is provided.

Each time one of the signals A. B. and C goes negative, the transmission gates controlled by that signal apply the outputs of their associated flip-flops to the decoder 25. With the particular frequencies shown, each of the lowest three units of time is thus signaled for a little over 1 millisecond after which the next unit of time is so signaled. The converted time-representative signals are applied to a set of seven driver transistors 27-1 through 27-7 which are typically on a separate bipolar integrated circuit chip. Each of the driving transistors 27 has its output connected to correspond- V ing segments of the three lowest order display digits of the multiplexed display 29. As seen in FIG. 2d. display 29 is comprised of a tens-of-hours stage 29s having two segments 91 as well as of a units-of-minutes. tens-ofminutes, and units-of-hours stage 29A, 29B, 29C, each comprised of seven segments 91. It is the last three stages which are multiplexed with the outputs of the units-of-minutes. tens-of-minutes. and units-of-hours counters 21a and 21b. For this purpose corresponding segments of the seven-segment display digits are connected in common to a single driver 27 so that. when a particular binary coded decimal signal is applied to the seven-segment decoder and it, in response thereto. energizes a desired combination of the drivers 27, those drivers will conditionally enable all three of the sevensegment display digits to display the number being signaled. However, since at any given instant in time there is only one unit of time which is being signaled and only one unit of time which should be displayed, means are provided to insure that only the proper one of the three seven-segment display digits will in fact be permitted to glow. This is the function of the display digit select transistors 31-2, -3, and -4, each of which is turned on by a respective one of the strobing signals A, B, and C in synchronism with the turning on of the respective 7 groups of transmission gates 81, 77, and 73. Accordingly, during each approximately 4 millisecond period. all three of the units-of-hours, tens-of-minutes, and

units-of-minutes are displayed in succession on respective ones of the three seven-segment display digits 29A, f

B. and C.

Each of the display digits 29A, 29B, and 29C consists of seven segments arranged in the outline of the FIG. 8. Each is connected at one of its two terminals to the collector of a display digit select transistor 31 and at its other terminal to the emitter of a particular one of seven driver transistors 27. y

- The tens-of-hours display digit 29s has only two segments 91 since only the terminal I is ever displayed. Thus. when a logic I is registered in the T flip-flop 39 of the hours counter 21]). the select transistor 31 is turned on and draws current through the segment 91 of the display digit 29s. For this reason the tens-of-hours display digit is not multiplexed with the other three display digits. Provision is made to compensate for the difference in brightness which might result from the fact that the tens-of-hours display digit 29s is displayed continually whereas the other three display digits are each displayed only one-third of the time. This may be done by an expedient as simple as the proper selection of the load resistors 93 connected to the tens-of-hours display segments 91. (Alternatively the tens-of-hours 1 might be turned on concurrently with one of the 3 strobing signals.)

Attention will next be directed to the divide-by-three circuit 17 whereby the strobing signals A. B, and C are produced in accordance with the present invention. In its preferred embodiment the divide-by-three counter comprises three single-stage shift registers 97A, 97B,

and 97C. Those illustrated herein are commonly referred to as D flip-flops. The following functional description will aid in understanding how the D flip-flop operates. Shift register 97A has a pair of outputs labelled Q and O which are logical opposites. It also has a pair of clock inputs Q and ;5 which are always clocked by signals of mutually opposite logic levels. The shift register also has an S set input (hence it is referred to as a set" shift register) and a D signal input. It is characteristic of the set shift register 97A that. if the signal at its S input is at logic 0. then, upon the negative going edge of the clock signal being applied at its d input, the output Q will take the logic state prevailing at the input D prior to the negative going clock transition. On the other hand. when its S input is at logic I. the Q output is forced to a logic I level and remains there even after the S input has returned to a logic 0 level. until the next negative going clock signal occurring when the D input is at logic 0.

The second and third one-stage shift registers 97B and 97 C may be similarly defined. They each have a Q and a Q output which are always logical opposites. a d) and d) clock input energized simiklrly to those of the first stage 97A, a D input and an R reset input (hence they are referred to as *reset shift registers). So long as the Ft reset input is at a logic 1 level. upon the negative going edge of the clock. the output Q will assume the state of the D input pre sent just prior tothat negative going edge. When the R input goes to logic 0 level, the Q output is forced to logic 0 and remains at logic 0 even after F returns to logic l. until the next negative going clock edge signal occurring when the D input is at logic l.

The clock signals for the 15 inputs of the three shift registers 97A, B. and C are derived from the output of the divide 2" counter 15 by a pair of series-connected inverters 98 and 99. The inverse of that 'clock signal is applied to the 4) inputs of the shift registers 97A-C through a transmission gate 100. The type of connection and the reason therefor is the same as that illustrated for the minutes counter 21a. The shift registers 97A-C are connected into a ring counter configuration by making a connection from the Q output of each registerto the D input of the next suchregister. Thus, register 97A drives 97B, 97B drives 97C, and 97C drives 97A. Finally. in order to eliminate undesirable combinations of logic states. the Q outputs of all three shift registers 97A-C are connected to the three inputs of an AND gate 101 and the Q outputs of the second and third flip-flops 97B and 97C are connected to inputs of a second AND gate 103. The outputs of the two logic gates 101 and 103 are applied to a NOR'gate 105 whose output is applied directly to the reset inputs R of the second and third shift registers 97B and 97C and whose inverted output is applied to the S input of the first shift register 97A through an inverter 107. It should be understood that L01, 103, and 105 are actually one complex gate, and that signals from 101 and 103 are not accessible.

FIG. 3 shows the 8 possible states which the shift registers 97A-C may randomly assume when the circuit begins operation. FIG. 3 also shows that 4 of those 8 states are detected by AND gate 103 and that the fifth state is detected by the AND gate 101. Provided the clock (I) is at logic 0, each of those AND gates is operative to eliminate any combination of register states which it detects. Assume, for example, that all three registers 97A C are in a logic 0 state, which is combination No. l in FIG. 3. This is detected by the AND gate 101, resulting in a logic 1 output therefrom which in turn is changed into a logic 0 output by the NOR gate 105. Applied to the Ii inputs of the reset shift registers 97B and 97C, the logic 0 signal at the output of the NOR gate 105 resets those shift register stages. Moreover, through the inverter 107 a logic 1 signal is applied to the set shift register 97A, causing it to be set. Thus, combination No. l is switched by means of the logic gates to combination No. 5 shown in FIG. 3.

Next, let it be assumed that combination No. 4 shown in FIG. 3 prevails, so that a logic 1 appears at the Q outputs of the reset flip-flops 97B and 97C, causing a logic '1 signal to appear at the output of AND gate 103. The result will be the same as that which followed the appearance of a logic 1 at the output of the AND gate 101. Consequently, the registers 97A-C will again be placed in their desired No. 5 combination shown in FIG. 3.

Further analysis of the circuit will show that each of the other undesired states Nos. 6, 7, and 8 will be detected by the AND gate 103. In some cases the detection is not immediate. For example, if the combination No. 6 prevails, it will not be immediately detected by the AND gate 103. Instead, the divide-by-three counter will be permitted to advance to its next logic state shown as combination No. 7. This combination is not detected either. but still another clock pulse leads to combination No. 4, which is detected by the AND gate 103 because of the presence of the logic I at the Q outputs of the reset shift registers 97B and 97C. This will then cause the counters to be placed in their No. 5

combination. Once the divide-by-three counter reaches 9 one of its desired states, that is, combinations Nos. 2, 3. and shown in FIG. 3, the detecting AND gates 103 and 101 play no further part in their operation. The shift register will automatically step through its three desired states, that is, combinations Nos. 2, 3, and 5 shown in FIG. 3, and will continue to do so.

It may be seen from the foregoing description of the divide-by-three circuit that the essence of its operation is to step it through those of its possible states in which one of its stages is at a given logic level and the other two of its stages are at the opposite logic level. Thus, in the exemplary circuit one of the shift registers 97 is always at a logic 1 state while the other two are always at a logic 0 state. In other words, a logic 1 is being circulated along with two logic Os through the stages of the counter. It will be apparent therefore, that the same desired effect could also be achieved by circulating a logic 0 and two logic is through the successive stages of the counter. The point to observe is that one of the three stages should be different from the other two so as to create at each of the three outputs associated with the three stages of the divide-by-three circuit a signal having a one-third duty cycle which is non-overlapping with the signals being produced by the other two such outputs.

What is claimed is:

1. In a digital watch the combination of:

a. means for generating timing signals;

b. a chain of binary dividers for reducing the frequency of said timing signals to no lower than one cycle per minute, said chain including a divide-bythree counter generating three differently phased timing signal trains, said divide-by-three counter including three cascaded single-stage shift registers and logic gating means for limiting the possible combination of their states to three;

c. a display including three multi-segment digits, each for displaying a different unit of time;

d. digital means for deriving from said one cycle per minute signal a separate binarily coded signal set to represent each of said units of time; and

e. means controlled by said timing signal trains for energizing in turn each of said three display digits with a decoded translation of the binarily coded signal set representing the unit of time assigned to that digit, said means for energizing including l. a single decoder for signalling different numberrepresentative segment-combinations in all of said digits in response to binarily coded signals representing different numbers,

signal trains for individually applying binarily coded signals representing different units of time in cyclic succession from said digital means to said decoder, and 3. display digit select means controlled by said timing signal trains for individually enabling in cyclic succession respective ones of said digits to be actuated in response to being signalled by said decoding means. 2. The combination of claim 1 characterized further in that said logic gating means has its inputs connected data digit select means controlled by said timing 10 to sense the presence of each of five different combinations of states in said shift registers, said logic gating means having its outputs operatively connected to inputs of said shift registers so as to cause them to be shifted out of said five states and into one of the said three states.

3. The combination of claim 2 characterized further in that said logic gating means comprises the logical equivalent of a pair of AND gates whose outputs are connected to said inputs of said shift registers through a NOR gate.

4. The combination of claim 1 characterized further in that in each of said combination of states a successive one of said three shift registers is at a given logic level while the other two shift registers are at a logic level different from said given logic level.

5. A digital watch having:

a. means for producing timing signals at a frequency greater than 1 Hz;

b. means for reducing the frequency of said timing signals to one cycle per minute;

c. a plurality of at least R cascaded registers for converting said one cycle per minute output into binarily coded signals representing successively larger units of time;

d. a display having R multi-segment digits, each for displaying a different one of said units of time;

e. decoding means for signalling selected numberrepresentative combinations of segments in all of said digits in response to selected combinations of binarily coded signals;

f. data digit select means for individually applying binarily coded signals representing different units of time from said registers to said decoder;

g. display digit select means for individually enabling respective ones of said digits to be activated in response to being signalled by said decoding means; and

. said watch being characterized by the fact that said means for reducing frequency includes a divide-by- R circuit operative to produce in cyclic succession R strobing signals of equal duration, each of said R signals having a duty cycle of 1 IR, with means being provided to apply said strobing signals to said data digit select means and to said display digit select means so as to actuate respective display digits in cyclic succession in synchronism with the application of their associated binarily coded data to said decoder, said divide-by-R circuit comprising three cascaded single stage shift registers and logic gating means connected between the outputs and the inputs of said shift registers so as to limit their total combination of permissible states to three.

6. The combination of claim 5 characterized further in that said logic gating means is operative to detect the presence of any of five different impermissible combinations of logic states and to cause said shift registers to shift out of these states into one of three different permissible combination of states which is not one of said five unpermissible combinations. 

1. In a digital watch the combination of: a. means for generating timing signals; b. a chain of binary dividers for reducing the frequency of said timing signals to no lower than one cycle per minute, said chain including a divide-by-three counter generating three differently phased timing signal trains, said divide-by-three counter including three cascaded single-stage shift registers and logic gating means for limiting the possible combination of their states to three; c. a display including three multi-segment digits, each for displaying a different unit of time; d. digital means for deriving from said one cycle per minute signal a separate binarily coded signal set to represent each of said units of time; and e. means controlled by said timing signal trains for energizing in turn each of said three display digits with a decoded translation of the binarily coded signal set representing the unit of time assigned to that digit, said means for energizing including
 1. a single decoder for signalling different numberrepresentative segment-combinations in all of said digits in response to binarily coded signals representing different numbers,
 2. data digit select means controlled by said timing signal trains for individually applying binarily coded signals representing different units of time in cyclic succession from said digital means to said decoder, and
 3. display digit select means controlled by said timing signal trains for individually enabling in cyclic succession respective ones of said digits to be actuated in response to being signalled by said decoding means.
 2. data digit select means controlled by said timing signal trains for individually applying binarily coded signals representing different units of time in cyclic succession from said digital means to said decoder, and
 2. The combination of claim 1 characterized further in that said logic gating means has its inputs connected to sense the presence of each of five different combinations of states in said shift registers, said logic gating means having its outputs operatively connected to inputs of said shift registers so as to cause them to be shifted out of said five states and into one of the said three states.
 3. The combination of claim 2 characterized further in that said logic gating means comprises the logical equivalent of a pair of AND gates whose outputs are connected to said inputs of said shift registers through a NOR gate.
 3. display digit select means controlled by said timing signal trains for individually enabling in cyclic succession respective ones of said digits to be actuated in response to being signalled by said decoding means.
 4. The combination of claim 1 characterized further in that in each of said combination of states a successive one of said three shift registers is at a given logic level while the other two shift registers are at a logic level different from said given logic level.
 5. A digital watch having: a. means for producing timing signals at a frequency greater than 1 Hz; b. means for reducing the frequency of said timing signals to one cycle per minute; c. a plurality of at least R cascaded registers for converting said one cycle per minute output into binarily coded signals representing successively larger units of time; d. a display having R multi-segment digits, each for displaying a different one of said units of time; e. decoding means for signalling selected number-representative combinations of segments in all of said digits in response to selected combinations of binarily coded signals; f. data digit select means for individually applying binarily coded signals representing different units of time from said registers to said decoder; g. display digit select means for individually enabling respective ones of said digits to be activated in response to being signalled by said decoding means; and h. said watch being characterized by the fact that said means for reducing frequency includes a divide-by-R circuit operative to produce in cyclic succession R strobing signaLs of equal duration, each of said R signals having a duty cycle of 1/R, with means being provided to apply said strobing signals to said data digit select means and to said display digit select means so as to actuate respective display digits in cyclic succession in synchronism with the application of their associated binarily coded data to said decoder, said divide-by-R circuit comprising three cascaded single stage shift registers and logic gating means connected between the outputs and the inputs of said shift registers so as to limit their total combination of permissible states to three.
 6. The combination of claim 5 characterized further in that said logic gating means is operative to detect the presence of any of five different impermissible combinations of logic states and to cause said shift registers to shift out of these states into one of three different permissible combination of states which is not one of said five unpermissible combinations. 